FIG. 1 shows a schematic diagram of a prior-art voltage-controlled oscillator (VCO) 100 having a ring of three differential delay stages 102a–c, where the differential outputs OUTP, OUTN of stage 102a are cross-connected (i.e., in an inverting manner) to the differential inputs INN, INP of stage 102b, the differential outputs OUTP, OUTN of stage 102b are cross-connected to the differential inputs INN, INP of stage 102c, and the differential outputs OUTP, OUTN of stage 102c are connected (i.e., in a non-inverting manner) to the differential inputs INP, INN of stage 102a. With this configuration of delay stages, a signal applied to the INP input of stage 102a passes around the ring twice before reaching the OUTP output of stage 102c, which corresponds to the VCOP output of VCO 100. Similarly, a signal applied to the INN input of stage 102a passes around the ring twice before reaching the OUTN output of stage 102c, which corresponds to the VCON output of VCO 100.
When the sum of the phase delays and the overall gain imparted by the different delay stages around the ring are appropriate values, then stable oscillation will occur within the ring. For example, if each of the three delay stages 102 in VCO 100 imparts a 60-degree phase delay and if each delay stage 102 has a gain of 1, then the total signal delay for two passes around the ring will equal 360 degrees and stable oscillation will occur within VCO 100.
As shown in FIG. 1, the differential outputs VCON, VCOP of VCO 100 are tapped off the outputs OUTN, OUTP from delay stage 102c. The frequency of the differential output signal is a function of the magnitude of the voltage control signal CONTROL applied to each delay stage. The higher the magnitude, the higher the frequency, at least within the operating frequency range of the VCO.
In some VCOs, such as VCO 100 of FIG. 1, that have a relatively wide operating frequency range, additional loading is applied at the output of each delay stage for the lower frequencies, while such loading is not applied at the higher frequencies. To provide this additional loading, VCO 100 has switch-controlled load circuitry connected to the outputs of each stage 102.
In particular, connected between power supply vdd and each output OUTN, OUTP of each stage 102, VCO 100 has a transistor (i.e., a MOSFET) 104 and a switch 106, where each MOSFET is configured with its gate connected to one side of the switch and its source, drain, and bulk connected to vdd. In such a configuration, each MOSFET provides a load corresponding to the MOSFET's gate capacitance, which is selectively applied to the corresponding delay stage output by the corresponding switch.
As indicated in FIG. 1, when VCO 100 is to be operated at a relatively low frequency (e.g., a frequency less than a specified threshold frequency level) within the VCO's operating frequency range, the control signal LOWFREQUENCY causes all of switches 106 to close, thereby applying the additional capacitive load of MOSFET 104 to the corresponding delay stage output. On the other hand, when VCO 100 is to be operated at a relatively high frequency, the control signal LOWFREQUENCY causes all of switches 106 to open, thereby removing the additional capacitive load of MOSFET 104 from the corresponding delay stage output. In this way, stable oscillation can be achieved over the entire operating frequency range of VCO 100.
One problem with the design of VCO 100 is that, if there is noise in the power supply vdd (or, alternatively, in the local ground), that noise will pass easily through MOSFETs 104 and switches 106 to the oscillator ring and potentially corrupt the operation of VCO 100 with undesirable levels of jitter in the differential outputs VCON, VCOP resulting from unwanted modulation of the otherwise stable oscillation within the ring.